65C02 CPU OpCodes: Difference between revisions

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(Created page with "{| class='wikitable' | ! width='25' | 0 ! width='25' | 1 ! width='25' | 2 ! width='25' | 3 ! width='25' | 4 ! width='25' | 5 ! width='25' | 6 ! width='25' | 7 ! width='25' | 8 ! width='25' | 9 ! width='25' | A ! width='25' | B ! width='25' | C ! width='25' | D ! width='25' | E ! width='25' | F |- ! 0x | align='center' | BRK | align='center' | ORA | align='center' | - | align='center' | - | align='center' | TRB | align='center' | ORA | align='center' | ASL | align='center...")
 
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|-
|-
! 0x
! 0x
| align='center' | BRK
| align='center' title='$00 Break' | [[OpCode - BRK|BRK]]
| align='center' | ORA
| align='center' title='$01 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | -
| align='center' title='$02 Invalid OpCode' | -
| align='center' | -
| align='center' title='$03 Invalid OpCode' | -
| align='center' | TRB
| align='center' title='$04 Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]]
| align='center' | ORA
| align='center' title='$05 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ASL
| align='center' title='$06 Arithmetic Shift Left' | [[OpCode - ASL|ASL]]
| align='center' | RMB0
| align='center' title='$07 Reset Memory Bit 0' | [[OpCode - RMB0|RMB0]]
| align='center' | PHP
| align='center' title='$08 Push Processor Status to Stack' | [[OpCode - PHP|PHP]]
| align='center' | ORA
| align='center' title='$09 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ASL
| align='center' title='$0A Arithmetic Shift Left' | [[OpCode - ASL|ASL]]
| align='center' | -
| align='center' title='$0B Invalid OpCode' | -
| align='center' | TSB
| align='center' title='$0C Test and Set Memory Bits with Accumulator' | [[OpCode - TSB|TSB]]
| align='center' | ORA
| align='center' title='$0D Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ASL
| align='center' title='$0E Arithmetic Shift Left' | [[OpCode - ASL|ASL]]
| align='center' | BBR0
| align='center' title='$0F Branch if Bit 0 Reset' | [[OpCode - BBR0|BBR0]]
|-
|-
! 1x
! 1x
| align='center' | BPL
| align='center' title='$10 Branch on Plus' | [[OpCode - BPL|BPL]]
| align='center' | ORA
| align='center' title='$11 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ORA
| align='center' title='$12 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | -
| align='center' title='$13 Invalid OpCode' | -
| align='center' | TRB
| align='center' title='$14 Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]]
| align='center' | ORA
| align='center' title='$15 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ASL
| align='center' title='$16 Arithmetic Shift Left' | [[OpCode - ASL|ASL]]
| align='center' | RMB1
| align='center' title='$17 Reset Memory Bit 1' | [[OpCode - RMB1|RMB1]]
| align='center' | CLC
| align='center' title='$18 Clear Carry' | [[OpCode - CLC|CLC]]
| align='center' | ORA
| align='center' title='$19 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | INC
| align='center' title='$1A Increment Accumulator' | [[OpCode - INC|INC]]
| align='center' | -
| align='center' title='$1B Invalid OpCode' | -
| align='center' | TRB
| align='center' title='$1C Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]]
| align='center' | ORA
| align='center' title='$1D Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]]
| align='center' | ASL
| align='center' title='$1E Arithmetic Shift Left' | [[OpCode - ASL|ASL]]
| align='center' | BBR1
| align='center' title='$1F Branch if Bit 1 Reset' | [[OpCode - BBR1|BBR1]]
|-
|-
! 2x
! 2x
| align='center' | JSR
| align='center' title='$20 Jump to Subroutine' | [[OpCode - JSR|JSR]]
| align='center' | AND
| align='center' title='$21 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | -
| align='center' title='$22 Invalid OpCode' | -
| align='center' | -
| align='center' title='$23 Invalid OpCode' | -
| align='center' | BIT
| align='center' title='$24 Test Bits' | [[OpCode - BIT|BIT]]
| align='center' | AND
| align='center' title='$25 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | ROL
| align='center' title='$26 Rotate Left' | [[OpCode - ROL|ROL]]
| align='center' | RMB2
| align='center' title='$27 Reset Memory Bit 2' | [[OpCode - RMB2|RMB2]]
| align='center' | PLP
| align='center' title='$28 Pull Processor Status from Stack' | [[OpCode - PLP|PLP]]
| align='center' | AND
| align='center' title='$29 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | ROL
| align='center' title='$2A Rotate Left' | [[OpCode - ROL|ROL]]
| align='center' | -
| align='center' title='$2B Invalid OpCode' | -
| align='center' | BIT
| align='center' title='$2C Test Bits' | [[OpCode - BIT|BIT]]
| align='center' | AND
| align='center' title='$2D Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | ROL
| align='center' title='$2E Rotate Left' | [[OpCode - ROL|ROL]]
| align='center' | BBR2
| align='center' title='$2F Branch if Bit 2 Reset' | [[OpCode - BBR2|BBR2]]
|-
|-
! 3x
! 3x
| align='center' | BMI
| align='center' title='$30 Branch on Minus' | [[OpCode - BMI|BMI]]
| align='center' | AND
| align='center' title='$31 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | AND
| align='center' title='$32 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | -
| align='center' title='$33 Invalid OpCode' | -
| align='center' | BIT
| align='center' title='$34 Test Bits' | [[OpCode - BIT|BIT]]
| align='center' | AND
| align='center' title='$35 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | ROL
| align='center' title='$36 Rotate Left' | [[OpCode - ROL|ROL]]
| align='center' | RMB3
| align='center' title='$37 Reset Memory Bit 3' | [[OpCode - RMB3|RMB3]]
| align='center' | SEC
| align='center' title='$38 Set Carry' | [[OpCode - SEC|SEC]]
| align='center' | AND
| align='center' title='$39 Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | DEC
| align='center' title='$3A Decrement Accumulator' | [[OpCode - DEC|DEC]]
| align='center' | -
| align='center' title='$3B Invalid OpCode' | -
| align='center' | BIT
| align='center' title='$3C Test Bits' | [[OpCode - BIT|BIT]]
| align='center' | AND
| align='center' title='$3D Bitwise AND with Accumulator' | [[OpCode - AND|AND]]
| align='center' | ROL
| align='center' title='$3E Rotate Left' | [[OpCode - ROL|ROL]]
| align='center' | BBR3
| align='center' title='$3F Branch if Bit 3 Reset' | [[OpCode - BBR3|BBR3]]
|-
|-
! 4x
! 4x
| align='center' | RTI
| align='center' title='$40 Return from Interrupt' | [[OpCode - RTI|RTI]]
| align='center' | EOR
| align='center' title='$41 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | -
| align='center' title='$42 Invalid OpCode' | -
| align='center' | -
| align='center' title='$43 Invalid OpCode' | -
| align='center' | -
| align='center' title='$44 Invalid OpCode' | -
| align='center' | EOR
| align='center' title='$45 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | LSR
| align='center' title='$46 Logical Shift Right' | [[OpCode - LSR|LSR]]
| align='center' | RMB4
| align='center' title='$47 Reset Memory Bit 4' | [[OpCode - RMB4|RMB4]]
| align='center' | PHA
| align='center' title='$48 Push Accumulator to Stack' | [[OpCode - PHA|PHA]]
| align='center' | EOR
| align='center' title='$49 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | LSR
| align='center' title='$4A Logical Shift Right' | [[OpCode - LSR|LSR]]
| align='center' | -
| align='center' title='$4B Invalid OpCode' | -
| align='center' | JMP
| align='center' title='$4C Jump' | [[OpCode - JMP|JMP]]
| align='center' | EOR
| align='center' title='$4D Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | LSR
| align='center' title='$4E Logical Shift Right' | [[OpCode - LSR|LSR]]
| align='center' | BBR4
| align='center' title='$4F Branch if Bit 4 Reset' | [[OpCode - BBR4|BBR4]]
|-
|-
! 5x
! 5x
| align='center' | BVC
| align='center' title='$50 Branch on Overflow Clear' | [[OpCode - BVC|BVC]]
| align='center' | EOR
| align='center' title='$51 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | EOR
| align='center' title='$52 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | -
| align='center' title='$53 Invalid OpCode' | -
| align='center' | -
| align='center' title='$54 Invalid OpCode' | -
| align='center' | EOR
| align='center' title='$55 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | LSR
| align='center' title='$56 Logical Shift Right' | [[OpCode - LSR|LSR]]
| align='center' | RMB5
| align='center' title='$57 Reset Memory Bit 5' | [[OpCode - RMB5|RMB5]]
| align='center' | CLI
| align='center' title='$58 Clear Interrupt' | [[OpCode - CLI|CLI]]
| align='center' | EOR
| align='center' title='$59 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | PHY
| align='center' title='$5A Push Y Register to Stack' | [[OpCode - PHY|PHY]]
| align='center' | -
| align='center' title='$5B Invalid OpCode' | -
| align='center' | -
| align='center' title='$5C Invalid OpCode' | -
| align='center' | EOR
| align='center' title='$5D Bitwise Exclusive OR' | [[OpCode - EOR|EOR]]
| align='center' | LSR
| align='center' title='$5E Logical Shift Right' | [[OpCode - LSR|LSR]]
| align='center' | BBR5
| align='center' title='$5F Branch if Bit 5 Reset' | [[OpCode - BBR5|BBR5]]
|-
|-
! 6x
! 6x
| align='center' | RTS
| align='center' title='$60 Return from Subroutine' | [[OpCode - RTS|RTS]]
| align='center' | ADC
| align='center' title='$61 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | -
| align='center' title='$62 Invalid OpCode' | -
| align='center' | -
| align='center' title='$63 Invalid OpCode' | -
| align='center' | STZ
| align='center' title='$64 Store Zero to Memory' | [[OpCode - STZ|STZ]]
| align='center' | ADC
| align='center' title='$65 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ROR
| align='center' title='$66 Rotate Right' | [[OpCode - ROR|ROR]]
| align='center' | RMB6
| align='center' title='$67 Reset Memory Bit 6' | [[OpCode - RMB6|RMB6]]
| align='center' | PLA
| align='center' title='$68 Pull Stack to Accumulator' | [[OpCode - PLA|PLA]]
| align='center' | ADC
| align='center' title='$69 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ROR
| align='center' title='$6A Rotate Right' | [[OpCode - ROR|ROR]]
| align='center' | -
| align='center' title='$6B Invalid OpCode' | -
| align='center' | JMP
| align='center' title='$6C Jump' | [[OpCode - JMP|JMP]]
| align='center' | ADC
| align='center' title='$6D Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ROR
| align='center' title='$6E Rotate Right' | [[OpCode - ROR|ROR]]
| align='center' | BBR6
| align='center' title='$6F Branch if Bit 6 Reset' | [[OpCode - BBR6|BBR6]]
|-
|-
! 7x
! 7x
| align='center' | BVS
| align='center' title='$70 Branch on Overflow Set' | [[OpCode - BVS|BVS]]
| align='center' | ADC
| align='center' title='$71 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ADC
| align='center' title='$72 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | -
| align='center' title='$73 Invalid OpCode' | -
| align='center' | STZ
| align='center' title='$74 Store Zero to Memory' | [[OpCode - STZ|STZ]]
| align='center' | ADC
| align='center' title='$75 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ROR
| align='center' title='$76 Rotate Right' | [[OpCode - ROR|ROR]]
| align='center' | RMB7
| align='center' title='$77 Reset Memory Bit 7' | [[OpCode - RMB7|RMB7]]
| align='center' | SEI
| align='center' title='$78 Set Interrupt' | [[OpCode - SEI|SEI]]
| align='center' | ADC
| align='center' title='$79 Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | PLY
| align='center' title='$7A Pull Register Y from Stack' | [[OpCode - PLY|PLY]]
| align='center' | -
| align='center' title='$7B Invalid OpCode' | -
| align='center' | JMP
| align='center' title='$7C Jump' | [[OpCode - JMP|JMP]]
| align='center' | ADC
| align='center' title='$7D Add with Carry' | [[OpCode - ADC|ADC]]
| align='center' | ROR
| align='center' title='$7E Rotate Right' | [[OpCode - ROR|ROR]]
| align='center' | BBR7
| align='center' title='$7F Branch if Bit 7 Reset' | [[OpCode - BBR7|BBR7]]
|-
|-
! 8x
! 8x
| align='center' | BRA
| align='center' title='$80 Branch Always' | [[OpCode - BRA|BRA]]
| align='center' | STA
| align='center' title='$81 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | -
| align='center' title='$82 Invalid OpCode' | -
| align='center' | -
| align='center' title='$83 Invalid OpCode' | -
| align='center' | STY
| align='center' title='$84 Store Y Register' | [[OpCode - STY|STY]]
| align='center' | STA
| align='center' title='$85 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | STX
| align='center' title='$86 Store X Register' | [[OpCode - STX|STX]]
| align='center' | SMB0
| align='center' title='$87 Set Memory Bit 0' | [[OpCode - SMB0|SMB0]]
| align='center' | DEY
| align='center' title='$88 Decrement Y Register' | [[OpCode - DEY|DEY]]
| align='center' | BIT
| align='center' title='$89 Test Bits' | [[OpCode - BIT|BIT]]
| align='center' | TXA
| align='center' title='$8A Transfer X Register to Accumulator' | [[OpCode - TXA|TXA]]
| align='center' | -
| align='center' title='$8B Invalid OpCode' | -
| align='center' | STY
| align='center' title='$8C Store Y Register' | [[OpCode - STY|STY]]
| align='center' | STA
| align='center' title='$8D Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | STX
| align='center' title='$8E Store X Register' | [[OpCode - STX|STX]]
| align='center' | BBS0
| align='center' title='$8F Branch if Bit 0 Set' | [[OpCode - BBS0|BBS0]]
|-
|-
! 9x
! 9x
| align='center' | BCC
| align='center' title='$90 Branch on Carry Clear' | [[OpCode - BCC|BCC]]
| align='center' | STA
| align='center' title='$91 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | STA
| align='center' title='$92 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | -
| align='center' title='$93 Invalid OpCode' | -
| align='center' | STY
| align='center' title='$94 Store Y Register' | [[OpCode - STY|STY]]
| align='center' | STA
| align='center' title='$95 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | STX
| align='center' title='$96 Store X Register' | [[OpCode - STX|STX]]
| align='center' | SMB1
| align='center' title='$97 Set Memory Bit 1' | [[OpCode - SMB1|SMB1]]
| align='center' | TYA
| align='center' title='$98 Transfer Y Register to Accumulator' | [[OpCode - TYA|TYA]]
| align='center' | STA
| align='center' title='$99 Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | TXS
| align='center' title='$9A Transfer X Register to Stack Pointer' | [[OpCode - TXS|TXS]]
| align='center' | -
| align='center' title='$9B Invalid OpCode' | -
| align='center' | STZ
| align='center' title='$9C Store Zero to Memory' | [[OpCode - STZ|STZ]]
| align='center' | STA
| align='center' title='$9D Store Accumulator' | [[OpCode - STA|STA]]
| align='center' | STZ
| align='center' title='$9E Store Zero to Memory' | [[OpCode - STZ|STZ]]
| align='center' | BBS1
| align='center' title='$9F Branch if Bit 1 Set' | [[OpCode - BBS1|BBS1]]
|-
|-
! Ax
! Ax
| align='center' | LDY
| align='center' title='$A0 Load Y Register' | [[OpCode - LDY|LDY]]
| align='center' | LDA
| align='center' title='$A1 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDX
| align='center' title='$A2 Load X Register' | [[OpCode - LDX|LDX]]
| align='center' | -
| align='center' title='$A3 Invalid OpCode' | -
| align='center' | LDY
| align='center' title='$A4 Load Y Register' | [[OpCode - LDY|LDY]]
| align='center' | LDA
| align='center' title='$A5 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDX
| align='center' title='$A6 Load X Register' | [[OpCode - LDX|LDX]]
| align='center' | SMB2
| align='center' title='$A7 Set Memory Bit 2' | [[OpCode - SMB2|SMB2]]
| align='center' | TAY
| align='center' title='$A8 Transfer Accumulator to Y Register' | [[OpCode - TAY|TAY]]
| align='center' | LDA
| align='center' title='$A9 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | TAX
| align='center' title='$AA Transfer Accumulator to X Register' | [[OpCode - TAX|TAX]]
| align='center' | -
| align='center' title='$AB Invalid OpCode' | -
| align='center' | LDY
| align='center' title='$AC Load Y Register' | [[OpCode - LDY|LDY]]
| align='center' | LDA
| align='center' title='$AD Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDX
| align='center' title='$AE Load X Register' | [[OpCode - LDX|LDX]]
| align='center' | BBS2
| align='center' title='$AF Branch if Bit 2 Set' | [[OpCode - BBS2|BBS2]]
|-
|-
! Bx
! Bx
| align='center' | BCS
| align='center' title='$B0 Branch on Carry Set' | [[OpCode - BCS|BCS]]
| align='center' | LDA
| align='center' title='$B1 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDA
| align='center' title='$B2 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | -
| align='center' title='$B3 Invalid OpCode' | -
| align='center' | LDY
| align='center' title='$B4 Load Y Register' | [[OpCode - LDY|LDY]]
| align='center' | LDA
| align='center' title='$B5 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDX
| align='center' title='$B6 Load X Register' | [[OpCode - LDX|LDX]]
| align='center' | SMB3
| align='center' title='$B7 Set Memory Bit 3' | [[OpCode - SMB3|SMB3]]
| align='center' | CLV
| align='center' title='$B8 Clear Overflow' | [[OpCode - CLV|CLV]]
| align='center' | LDA
| align='center' title='$B9 Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | TSX
| align='center' title='$BA Transfer Stack Pointer to X Register' | [[OpCode - TSX|TSX]]
| align='center' | -
| align='center' title='$BB Invalid OpCode' | -
| align='center' | LDY
| align='center' title='$BC Load Y Register' | [[OpCode - LDY|LDY]]
| align='center' | LDA
| align='center' title='$BD Load Accumulator' | [[OpCode - LDA|LDA]]
| align='center' | LDX
| align='center' title='$BE Load X Register' | [[OpCode - LDX|LDX]]
| align='center' | BBS3
| align='center' title='$BF Branch if Bit 3 Set' | [[OpCode - BBS3|BBS3]]
|-
|-
! Cx
! Cx
| align='center' | CPY
| align='center' title='$C0 Compare with Y Register' | [[OpCode - CPY|CPY]]
| align='center' | CMP
| align='center' title='$C1 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | -
| align='center' title='$C2 Invalid OpCode' | -
| align='center' | -
| align='center' title='$C3 Invalid OpCode' | -
| align='center' | CPY
| align='center' title='$C4 Compare with Y Register' | [[OpCode - CPY|CPY]]
| align='center' | CMP
| align='center' title='$C5 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | DEC
| align='center' title='$C6 Decrement Memory' | [[OpCode - DEC|DEC]]
| align='center' | SMB4
| align='center' title='$C7 Set Memory Bit 4' | [[OpCode - SMB4|SMB4]]
| align='center' | INY
| align='center' title='$C8 Increment Y Register' | [[OpCode - INY|INY]]
| align='center' | CMP
| align='center' title='$C9 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | DEX
| align='center' title='$CA Decrement X Register' | [[OpCode - DEX|DEX]]
| align='center' | WAI
| align='center' title='$CB Wait for Interrupt' | [[OpCode - WAI|WAI]]
| align='center' | CPY
| align='center' title='$CC Compare with Y Register' | [[OpCode - CPY|CPY]]
| align='center' | CMP
| align='center' title='$CD Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | DEC
| align='center' title='$CE Decrement Memory' | [[OpCode - DEC|DEC]]
| align='center' | BBS4
| align='center' title='$CF Branch if Bit 4 Set' | [[OpCode - BBS4|BBS4]]
|-
|-
! Dx
! Dx
| align='center' | BNE
| align='center' title='$D0 Branch on Not Equal' | [[OpCode - BNE|BNE]]
| align='center' | CMP
| align='center' title='$D1 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | CMP
| align='center' title='$D2 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | -
| align='center' title='$D3 Invalid OpCode' | -
| align='center' | -
| align='center' title='$D4 Invalid OpCode' | -
| align='center' | CMP
| align='center' title='$D5 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | DEC
| align='center' title='$D6 Decrement Memory' | [[OpCode - DEC|DEC]]
| align='center' | SMB5
| align='center' title='$D7 Set Memory Bit 5' | [[OpCode - SMB5|SMB5]]
| align='center' | CLD
| align='center' title='$D8 Clear Decimal' | [[OpCode - CLD|CLD]]
| align='center' | CMP
| align='center' title='$D9 Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | PHX
| align='center' title='$DA Push X Register to Stack' | [[OpCode - PHX|PHX]]
| align='center' | STP
| align='center' title='$DB Stop until CPU Reset' | [[OpCode - STP|STP]]
| align='center' | -
| align='center' title='$DC Invalid OpCode' | -
| align='center' | CMP
| align='center' title='$DD Compare with Accumulator' | [[OpCode - CMP|CMP]]
| align='center' | DEC
| align='center' title='$DE Decrement Memory' | [[OpCode - DEC|DEC]]
| align='center' | BBS5
| align='center' title='$DF Branch if Bit 5 Set' | [[OpCode - BBS5|BBS5]]
|-
|-
! Ex
! Ex
| align='center' | CPX
| align='center' title='$E0 Compare with X Register' | [[OpCode - CPX|CPX]]
| align='center' | SBC
| align='center' title='$E1 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | -
| align='center' title='$E2 Invalid OpCode' | -
| align='center' | -
| align='center' title='$E3 Invalid OpCode' | -
| align='center' | CPX
| align='center' title='$E4 Compare with X Register' | [[OpCode - CPX|CPX]]
| align='center' | SBC
| align='center' title='$E5 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | INC
| align='center' title='$E6 Increment Memory' | [[OpCode - INC|INC]]
| align='center' | SMB6
| align='center' title='$E7 Set Memory Bit 6' | [[OpCode - SMB6|SMB6]]
| align='center' | INX
| align='center' title='$E8 Increment X Register' | [[OpCode - INX|INX]]
| align='center' | SBC
| align='center' title='$E9 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | NOP
| align='center' title='$EA No Operation' | [[OpCode - NOP|NOP]]
| align='center' | -
| align='center' title='$EB Invalid OpCode' | -
| align='center' | CPX
| align='center' title='$EC Compare with X Register' | [[OpCode - CPX|CPX]]
| align='center' | SBC
| align='center' title='$ED Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | INC
| align='center' title='$EE Increment Memory' | [[OpCode - INC|INC]]
| align='center' | BBS6
| align='center' title='$EF Branch if Bit 6 Set' | [[OpCode - BBS6|BBS6]]
|-
|-
! Fx
! Fx
| align='center' | BEQ
| align='center' title='$F0 Branch on Equal' | [[OpCode - BEQ|BEQ]]
| align='center' | SBC
| align='center' title='$F1 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | SBC
| align='center' title='$F2 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | -
| align='center' title='$F3 Invalid OpCode' | -
| align='center' | -
| align='center' title='$F4 Invalid OpCode' | -
| align='center' | SBC
| align='center' title='$F5 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | INC
| align='center' title='$F6 Increment Memory' | [[OpCode - INC|INC]]
| align='center' | SMB7
| align='center' title='$F7 Set Memory Bit 7' | [[OpCode - SMB7|SMB7]]
| align='center' | SED
| align='center' title='$F8 Set Decimal' | [[OpCode - SED|SED]]
| align='center' | SBC
| align='center' title='$F9 Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | PLX
| align='center' title='$FA Pull X Register from Stack' | [[OpCode - PLX|PLX]]
| align='center' | -
| align='center' title='$FB Invalid OpCode' | -
| align='center' | -
| align='center' title='$FC Invalid OpCode' | -
| align='center' | SBC
| align='center' title='$FD Subtract with Carry' | [[OpCode - SBC|SBC]]
| align='center' | INC
| align='center' title='$FE Increment Memory' | [[OpCode - INC|INC]]
| align='center' | BBS7
| align='center' title='$FF Branch if Bit 7 Set' | [[OpCode - BBS7|BBS7]]
|}
|}
Head over to the [[Chip - 65C02 CPU|65C02 CPU]] or to the [[65C02 CPU Address Modes|Address Modes]].

Latest revision as of 19:41, 31 January 2024

0 1 2 3 4 5 6 7 8 9 A B C D E F
0x BRK ORA - - TRB ORA ASL RMB0 PHP ORA ASL - TSB ORA ASL BBR0
1x BPL ORA ORA - TRB ORA ASL RMB1 CLC ORA INC - TRB ORA ASL BBR1
2x JSR AND - - BIT AND ROL RMB2 PLP AND ROL - BIT AND ROL BBR2
3x BMI AND AND - BIT AND ROL RMB3 SEC AND DEC - BIT AND ROL BBR3
4x RTI EOR - - - EOR LSR RMB4 PHA EOR LSR - JMP EOR LSR BBR4
5x BVC EOR EOR - - EOR LSR RMB5 CLI EOR PHY - - EOR LSR BBR5
6x RTS ADC - - STZ ADC ROR RMB6 PLA ADC ROR - JMP ADC ROR BBR6
7x BVS ADC ADC - STZ ADC ROR RMB7 SEI ADC PLY - JMP ADC ROR BBR7
8x BRA STA - - STY STA STX SMB0 DEY BIT TXA - STY STA STX BBS0
9x BCC STA STA - STY STA STX SMB1 TYA STA TXS - STZ STA STZ BBS1
Ax LDY LDA LDX - LDY LDA LDX SMB2 TAY LDA TAX - LDY LDA LDX BBS2
Bx BCS LDA LDA - LDY LDA LDX SMB3 CLV LDA TSX - LDY LDA LDX BBS3
Cx CPY CMP - - CPY CMP DEC SMB4 INY CMP DEX WAI CPY CMP DEC BBS4
Dx BNE CMP CMP - - CMP DEC SMB5 CLD CMP PHX STP - CMP DEC BBS5
Ex CPX SBC - - CPX SBC INC SMB6 INX SBC NOP - CPX SBC INC BBS6
Fx BEQ SBC SBC - - SBC INC SMB7 SED SBC PLX - - SBC INC BBS7

Head over to the 65C02 CPU or to the Address Modes.

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