Integrated Circuit Chips: Difference between revisions

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= Processor =
= Processor =
== 65C02 ==
== 65C02 ==
= RAM =
= RAM =
== 32KB ==
== AS6C62256 ==
== 512KB ==
This 32KB RAM chip is used for NerdConsole's 16KB of Main RAM.  There aren't any readily available 16KB static RAM chips, so the decision was made to use a 32KB chip instead, and only use half of it.  Main RAM was intentionally placed on a separate chip from Extended RAM to simplify bank selecting logic.
 
{| class="wikitable"
| style="text-align:right" width="180" | A14
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 28
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | A12
! style="text-align:left" | 2
! style="text-align:right" | 27
| style="text-align:left" | ~WE
|-
| style="text-align:right" | A7
! style="text-align:left" | 3
! style="text-align:right" | 26
| style="text-align:left" | A13
|-
| style="text-align:right" | A6
! style="text-align:left" | 4
! style="text-align:right" | 25
| style="text-align:left" | A8
|-
| style="text-align:right" | A5
! style="text-align:left" | 5
! style="text-align:right" | 24
| style="text-align:left" | A9
|-
| style="text-align:right" | A4
! style="text-align:left" | 6
! style="text-align:right" | 23
| style="text-align:left" | A11
|-
| style="text-align:right" | A3
! style="text-align:left" | 7
! style="text-align:right" | 22
| style="text-align:left" | ~OE
|-
| style="text-align:right" | A2
! style="text-align:left" | 8
! style="text-align:right" | 21
| style="text-align:left" | A10
|-
| style="text-align:right" | A1
! style="text-align:left" | 9
! style="text-align:right" | 20
| style="text-align:left" | ~CE
|-
| style="text-align:right" | A0
! style="text-align:left" | 10
! style="text-align:right" | 19
| style="text-align:left" | D7
|-
| style="text-align:right" | D0
! style="text-align:left" | 11
! style="text-align:right" | 18
| style="text-align:left" | D6
|-
| style="text-align:right" | D1
! style="text-align:left" | 12
! style="text-align:right" | 17
| style="text-align:left" | D5
|-
| style="text-align:right" | D2
! style="text-align:left" | 13
! style="text-align:right" | 16
| style="text-align:left" | D4
|-
| style="text-align:right" | GND
! style="text-align:left" | 14
! style="text-align:right" | 15
| style="text-align:left" | D3
|}
 
== AS6C4008 ==
This 512KB RAM chip is used for Extended RAM and provides 32x 16KB banks.
 
{| class="wikitable"
| style="text-align:right" width="180" | A18
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 32
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | A16
! style="text-align:left" | 2
! style="text-align:right" | 31
| style="text-align:left" | A15
|-
| style="text-align:right" | A14
! style="text-align:left" | 3
! style="text-align:right" | 30
| style="text-align:left" | A17
|-
| style="text-align:right" | A12
! style="text-align:left" | 4
! style="text-align:right" | 29
| style="text-align:left" | ~WE
|-
| style="text-align:right" | A7
! style="text-align:left" | 5
! style="text-align:right" | 28
| style="text-align:left" | A13
|-
| style="text-align:right" | A6
! style="text-align:left" | 6
! style="text-align:right" | 27
| style="text-align:left" | A8
|-
| style="text-align:right" | A5
! style="text-align:left" | 7
! style="text-align:right" | 26
| style="text-align:left" | A9
|-
| style="text-align:right" | A4
! style="text-align:left" | 8
! style="text-align:right" | 25
| style="text-align:left" | A11
|-
| style="text-align:right" | A3
! style="text-align:left" | 9
! style="text-align:right" | 24
| style="text-align:left" | ~OE
|-
| style="text-align:right" | A2
! style="text-align:left" | 10
! style="text-align:right" | 23
| style="text-align:left" | A10
|-
| style="text-align:right" | A1
! style="text-align:left" | 11
! style="text-align:right" | 22
| style="text-align:left" | ~CE
|-
| style="text-align:right" | A0
! style="text-align:left" | 12
! style="text-align:right" | 21
| style="text-align:left" | D7
|-
| style="text-align:right" | D0
! style="text-align:left" | 13
! style="text-align:right" | 20
| style="text-align:left" | D6
|-
| style="text-align:right" | D1
! style="text-align:left" | 14
! style="text-align:right" | 19
| style="text-align:left" | D5
|-
| style="text-align:right" | D2
! style="text-align:left" | 15
! style="text-align:right" | 18
| style="text-align:left" | D4
|-
| style="text-align:right" | GND
! style="text-align:left" | 16
! style="text-align:right" | 17
| style="text-align:left" | D3
|}
 
= ROM =
= ROM =
Several different types of ROM chips can be used for cartridges.
== 8KB ==
== 8KB ==
== 32KB ==
== 32KB ==
Line 12: Line 172:
== 256KB ==
== 256KB ==
== 512KB ==
== 512KB ==
= Audio =
= Audio =
== YM-3812 ==
== YM-3812 ==
== YM-3014 ==
== YM-3014 ==
= Logic =
= Logic =
NerdConsole uses a variety of logic chips for address decoding, holding register values, and buffering data as it moves between systems.
== 74HCT00 ==
== 74HCT00 ==
This chip provides four 2-input NAND gates.
{| class="wikitable"
| style="text-align:right" width="180" | 1A
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 14
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1B
! style="text-align:left" | 2
! style="text-align:right" | 13
| style="text-align:left" | 4B
|-
| style="text-align:right" | 1Y
! style="text-align:left" | 3
! style="text-align:right" | 12
| style="text-align:left" | 4A
|-
| style="text-align:right" | 2A
! style="text-align:left" | 4
! style="text-align:right" | 11
| style="text-align:left" | 4Y
|-
| style="text-align:right" | 2B
! style="text-align:left" | 5
! style="text-align:right" | 10
| style="text-align:left" | 3B
|-
| style="text-align:right" | 2Y
! style="text-align:left" | 6
! style="text-align:right" | 9
| style="text-align:left" | 3A
|-
| style="text-align:right" | GND
! style="text-align:left" | 7
! style="text-align:right" | 8
| style="text-align:left" | 3Y
|}
== 74HCT08 ==
== 74HCT08 ==
This chip provides four 2-input AND gates.
{| class="wikitable"
| style="text-align:right" width="180" | 1A
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 14
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1B
! style="text-align:left" | 2
! style="text-align:right" | 13
| style="text-align:left" | 4B
|-
| style="text-align:right" | 1Y
! style="text-align:left" | 3
! style="text-align:right" | 12
| style="text-align:left" | 4A
|-
| style="text-align:right" | 2A
! style="text-align:left" | 4
! style="text-align:right" | 11
| style="text-align:left" | 4Y
|-
| style="text-align:right" | 2B
! style="text-align:left" | 5
! style="text-align:right" | 10
| style="text-align:left" | 3B
|-
| style="text-align:right" | 2Y
! style="text-align:left" | 6
! style="text-align:right" | 9
| style="text-align:left" | 3A
|-
| style="text-align:right" | GND
! style="text-align:left" | 7
! style="text-align:right" | 8
| style="text-align:left" | 3Y
|}
== 74HCT14 ==
== 74HCT14 ==
This chip provides six signal inverters.
{| class="wikitable"
| style="text-align:right" width="180" | 1A
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 14
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1Y
! style="text-align:left" | 2
! style="text-align:right" | 13
| style="text-align:left" | 6A
|-
| style="text-align:right" | 2A
! style="text-align:left" | 3
! style="text-align:right" | 12
| style="text-align:left" | 6Y
|-
| style="text-align:right" | 2Y
! style="text-align:left" | 4
! style="text-align:right" | 11
| style="text-align:left" | 5A
|-
| style="text-align:right" | 3A
! style="text-align:left" | 5
! style="text-align:right" | 10
| style="text-align:left" | 5Y
|-
| style="text-align:right" | 3Y
! style="text-align:left" | 6
! style="text-align:right" | 9
| style="text-align:left" | 4A
|-
| style="text-align:right" | GND
! style="text-align:left" | 7
! style="text-align:right" | 8
| style="text-align:left" | 4Y
|}
== 74HCT30 ==
This chip provides a single 8-input NAND gate.  This is used to identify when extended RAM bank 255 is selected and thus extended RAM writes should instead be directed to the PPU.
{| class="wikitable"
| style="text-align:right" width="180" | A
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 14
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | B
! style="text-align:left" | 2
! style="text-align:right" | 13
| style="text-align:left" | NC
|-
| style="text-align:right" | C
! style="text-align:left" | 3
! style="text-align:right" | 12
| style="text-align:left" | H
|-
| style="text-align:right" | D
! style="text-align:left" | 4
! style="text-align:right" | 11
| style="text-align:left" | G
|-
| style="text-align:right" | E
! style="text-align:left" | 5
! style="text-align:right" | 10
| style="text-align:left" | NC
|-
| style="text-align:right" | F
! style="text-align:left" | 6
! style="text-align:right" | 9
| style="text-align:left" | NC
|-
| style="text-align:right" | GND
! style="text-align:left" | 7
! style="text-align:right" | 8
| style="text-align:left" | Y
|}
== 74HCT32 ==
This chip provides four 2-input OR gates.
{| class="wikitable"
| style="text-align:right" width="180" | 1A
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 14
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1B
! style="text-align:left" | 2
! style="text-align:right" | 13
| style="text-align:left" | 4B
|-
| style="text-align:right" | 1Y
! style="text-align:left" | 3
! style="text-align:right" | 12
| style="text-align:left" | 4A
|-
| style="text-align:right" | 2A
! style="text-align:left" | 4
! style="text-align:right" | 11
| style="text-align:left" | 4Y
|-
| style="text-align:right" | 2B
! style="text-align:left" | 5
! style="text-align:right" | 10
| style="text-align:left" | 3B
|-
| style="text-align:right" | 2Y
! style="text-align:left" | 6
! style="text-align:right" | 9
| style="text-align:left" | 3A
|-
| style="text-align:right" | GND
! style="text-align:left" | 7
! style="text-align:right" | 8
| style="text-align:left" | 3Y
|}
== 74HCT139 ==
This chip is provides 2 separate 2 to 4 line decoders.  Each takes 2 inputs as a 2-bit number (0-3) and turns on the single line that corresponds to that number as output.
{| class="wikitable"
| style="text-align:right" width="180" | ~1G
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 16
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1A
! style="text-align:left" | 2
! style="text-align:right" | 15
| style="text-align:left" | ~2G
|-
| style="text-align:right" | 1B
! style="text-align:left" | 3
! style="text-align:right" | 14
| style="text-align:left" | 2A
|-
| style="text-align:right" | 1Y0
! style="text-align:left" | 4
! style="text-align:right" | 13
| style="text-align:left" | 2B
|-
| style="text-align:right" | 1Y1
! style="text-align:left" | 5
! style="text-align:right" | 12
| style="text-align:left" | 2Y0
|-
| style="text-align:right" | 1Y2
! style="text-align:left" | 6
! style="text-align:right" | 11
| style="text-align:left" | 2Y1
|-
| style="text-align:right" | 1Y3
! style="text-align:left" | 7
! style="text-align:right" | 10
| style="text-align:left" | 2Y2
|-
| style="text-align:right" | GND
! style="text-align:left" | 8
! style="text-align:right" | 9
| style="text-align:left" | 2Y3
|}
== 74HCT238 ==
This chip is a 3 to 8 line decoder.  It takes 3 inputs as a 3-bit number (0-7) and turns on the single line that corresponds to that number as output.
{| class="wikitable"
| style="text-align:right" width="180" | A0
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 16
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | A1
! style="text-align:left" | 2
! style="text-align:right" | 15
| style="text-align:left" | Y0
|-
| style="text-align:right" | A2
! style="text-align:left" | 3
! style="text-align:right" | 14
| style="text-align:left" | Y1
|-
| style="text-align:right" | ~G0
! style="text-align:left" | 4
! style="text-align:right" | 13
| style="text-align:left" | Y2
|-
| style="text-align:right" | ~G1
! style="text-align:left" | 5
! style="text-align:right" | 12
| style="text-align:left" | Y3
|-
| style="text-align:right" | G2
! style="text-align:left" | 6
! style="text-align:right" | 11
| style="text-align:left" | Y4
|-
| style="text-align:right" | Y7
! style="text-align:left" | 7
! style="text-align:right" | 10
| style="text-align:left" | Y5
|-
| style="text-align:right" | GND
! style="text-align:left" | 8
! style="text-align:right" | 9
| style="text-align:left" | Y6
|}
== 74HCT240 ==
This chip reads the state of all 8 possible controllers and inverts the signal turning the 0s from pressed buttons into 1s.
{| class="wikitable"
| style="text-align:right" width="180" | ~1OE
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 20
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1A0
! style="text-align:left" | 2
! style="text-align:right" | 19
| style="text-align:left" | ~2OE
|-
| style="text-align:right" | ~2Y3
! style="text-align:left" | 3
! style="text-align:right" | 18
| style="text-align:left" | ~1Y0
|-
| style="text-align:right" | 1A1
! style="text-align:left" | 4
! style="text-align:right" | 17
| style="text-align:left" | 2A3
|-
| style="text-align:right" | ~2Y2
! style="text-align:left" | 5
! style="text-align:right" | 16
| style="text-align:left" | ~1Y1
|-
| style="text-align:right" | 1A2
! style="text-align:left" | 6
! style="text-align:right" | 15
| style="text-align:left" | 2A2
|-
| style="text-align:right" | ~2Y1
! style="text-align:left" | 7
! style="text-align:right" | 14
| style="text-align:left" | ~1Y2
|-
| style="text-align:right" | 1A3
! style="text-align:left" | 8
! style="text-align:right" | 13
| style="text-align:left" | 2A1
|-
| style="text-align:right" | ~2Y0
! style="text-align:left" | 9
! style="text-align:right" | 12
| style="text-align:left" | ~1Y3
|-
| style="text-align:right" | GND
! style="text-align:left" | 10
! style="text-align:right" | 11
| style="text-align:left" | 2A0
|}
== 74HCT273 ==
== 74HCT273 ==
This chip provides an octal D-type flip-flops with a clear pin for ensuring a known state upon system reset.  These are commonly used for holding upper address pin values for bank selection.
{| class="wikitable"
| style="text-align:right" width="180" | ~CLR
! style="text-align:left" width="30" | 1
! style="text-align:right" width="30" | 20
| style="text-align:left" width="180" | VCC
|-
| style="text-align:right" | 1Q
! style="text-align:left" | 2
! style="text-align:right" | 19
| style="text-align:left" | 8Q
|-
| style="text-align:right" | 1D
! style="text-align:left" | 3
! style="text-align:right" | 18
| style="text-align:left" | 8D
|-
| style="text-align:right" | 2D
! style="text-align:left" | 4
! style="text-align:right" | 17
| style="text-align:left" | 7D
|-
| style="text-align:right" | 2Q
! style="text-align:left" | 5
! style="text-align:right" | 16
| style="text-align:left" | 7Q
|-
| style="text-align:right" | 3Q
! style="text-align:left" | 6
! style="text-align:right" | 15
| style="text-align:left" | 6Q
|-
| style="text-align:right" | 3D
! style="text-align:left" | 7
! style="text-align:right" | 14
| style="text-align:left" | 6D
|-
| style="text-align:right" | 4D
! style="text-align:left" | 8
! style="text-align:right" | 13
| style="text-align:left" | 5D
|-
| style="text-align:right" | 4Q
! style="text-align:left" | 9
! style="text-align:right" | 12
| style="text-align:left" | 5Q
|-
| style="text-align:right" | GND
! style="text-align:left" | 10
! style="text-align:right" | 11
| style="text-align:left" | CLK
|}

Revision as of 19:35, 21 January 2024

This is a collection of pinouts and basic descriptions for all of the various chips used in NerdConsole.

Processor

65C02

RAM

AS6C62256

This 32KB RAM chip is used for NerdConsole's 16KB of Main RAM. There aren't any readily available 16KB static RAM chips, so the decision was made to use a 32KB chip instead, and only use half of it. Main RAM was intentionally placed on a separate chip from Extended RAM to simplify bank selecting logic.

A14 1 28 VCC
A12 2 27 ~WE
A7 3 26 A13
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 ~OE
A2 8 21 A10
A1 9 20 ~CE
A0 10 19 D7
D0 11 18 D6
D1 12 17 D5
D2 13 16 D4
GND 14 15 D3

AS6C4008

This 512KB RAM chip is used for Extended RAM and provides 32x 16KB banks.

A18 1 32 VCC
A16 2 31 A15
A14 3 30 A17
A12 4 29 ~WE
A7 5 28 A13
A6 6 27 A8
A5 7 26 A9
A4 8 25 A11
A3 9 24 ~OE
A2 10 23 A10
A1 11 22 ~CE
A0 12 21 D7
D0 13 20 D6
D1 14 19 D5
D2 15 18 D4
GND 16 17 D3

ROM

Several different types of ROM chips can be used for cartridges.

8KB

32KB

64KB

128KB

256KB

512KB

Audio

YM-3812

YM-3014

Logic

NerdConsole uses a variety of logic chips for address decoding, holding register values, and buffering data as it moves between systems.

74HCT00

This chip provides four 2-input NAND gates.

1A 1 14 VCC
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y

74HCT08

This chip provides four 2-input AND gates.

1A 1 14 VCC
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y

74HCT14

This chip provides six signal inverters.

1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y

74HCT30

This chip provides a single 8-input NAND gate. This is used to identify when extended RAM bank 255 is selected and thus extended RAM writes should instead be directed to the PPU.

A 1 14 VCC
B 2 13 NC
C 3 12 H
D 4 11 G
E 5 10 NC
F 6 9 NC
GND 7 8 Y

74HCT32

This chip provides four 2-input OR gates.

1A 1 14 VCC
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y

74HCT139

This chip is provides 2 separate 2 to 4 line decoders. Each takes 2 inputs as a 2-bit number (0-3) and turns on the single line that corresponds to that number as output.

~1G 1 16 VCC
1A 2 15 ~2G
1B 3 14 2A
1Y0 4 13 2B
1Y1 5 12 2Y0
1Y2 6 11 2Y1
1Y3 7 10 2Y2
GND 8 9 2Y3

74HCT238

This chip is a 3 to 8 line decoder. It takes 3 inputs as a 3-bit number (0-7) and turns on the single line that corresponds to that number as output.

A0 1 16 VCC
A1 2 15 Y0
A2 3 14 Y1
~G0 4 13 Y2
~G1 5 12 Y3
G2 6 11 Y4
Y7 7 10 Y5
GND 8 9 Y6

74HCT240

This chip reads the state of all 8 possible controllers and inverts the signal turning the 0s from pressed buttons into 1s.

~1OE 1 20 VCC
1A0 2 19 ~2OE
~2Y3 3 18 ~1Y0
1A1 4 17 2A3
~2Y2 5 16 ~1Y1
1A2 6 15 2A2
~2Y1 7 14 ~1Y2
1A3 8 13 2A1
~2Y0 9 12 ~1Y3
GND 10 11 2A0

74HCT273

This chip provides an octal D-type flip-flops with a clear pin for ensuring a known state upon system reset. These are commonly used for holding upper address pin values for bank selection.

~CLR 1 20 VCC
1Q 2 19 8Q
1D 3 18 8D
2D 4 17 7D
2Q 5 16 7Q
3Q 6 15 6Q
3D 7 14 6D
4D 8 13 5D
4Q 9 12 5Q
GND 10 11 CLK
Retrieved from "http://wiki.nerdconsole.com:80/index.php?title=Integrated_Circuit_Chips&oldid=349"