65C02 CPU OpCodes: Difference between revisions
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! 0x | ! 0x | ||
| align='center' title='$00' | [[OpCode - BRK|BRK]] | | align='center' title='$00 Break' | [[OpCode - BRK|BRK]] | ||
| align='center' title='$01' | [[OpCode - ORA|ORA]] | | align='center' title='$01 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$02 Invalid OpCode' | - | | align='center' title='$02 Invalid OpCode' | - | ||
| align='center' title='$03 Invalid OpCode' | - | | align='center' title='$03 Invalid OpCode' | - | ||
| align='center' title='$04' | [[OpCode - TRB|TRB]] | | align='center' title='$04 Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]] | ||
| align='center' title='$05' | [[OpCode - ORA|ORA]] | | align='center' title='$05 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$06' | [[OpCode - ASL|ASL]] | | align='center' title='$06 Arithmetic Shift Left' | [[OpCode - ASL|ASL]] | ||
| align='center' title='$07' | [[OpCode - RMB0|RMB0]] | | align='center' title='$07 Reset Memory Bit 0' | [[OpCode - RMB0|RMB0]] | ||
| align='center' title='$08' | [[OpCode - PHP|PHP]] | | align='center' title='$08 Push Processor Status to Stack' | [[OpCode - PHP|PHP]] | ||
| align='center' title='$09' | [[OpCode - ORA|ORA]] | | align='center' title='$09 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$0A' | [[OpCode - ASL|ASL]] | | align='center' title='$0A Arithmetic Shift Left' | [[OpCode - ASL|ASL]] | ||
| align='center' title='$0B Invalid OpCode' | - | | align='center' title='$0B Invalid OpCode' | - | ||
| align='center' title='$0C' | [[OpCode - TSB|TSB]] | | align='center' title='$0C Test and Set Memory Bits with Accumulator' | [[OpCode - TSB|TSB]] | ||
| align='center' title='$0D' | [[OpCode - ORA|ORA]] | | align='center' title='$0D Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$0E' | [[OpCode - ASL|ASL]] | | align='center' title='$0E Arithmetic Shift Left' | [[OpCode - ASL|ASL]] | ||
| align='center' title='$0F' | [[OpCode - BBR0|BBR0]] | | align='center' title='$0F Branch if Bit 0 Reset' | [[OpCode - BBR0|BBR0]] | ||
|- | |- | ||
! 1x | ! 1x | ||
| align='center' title='$10' | [[OpCode - BPL|BPL]] | | align='center' title='$10 Branch on Plus' | [[OpCode - BPL|BPL]] | ||
| align='center' title='$11' | [[OpCode - ORA|ORA]] | | align='center' title='$11 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$12' | [[OpCode - ORA|ORA]] | | align='center' title='$12 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$13 Invalid OpCode' | - | | align='center' title='$13 Invalid OpCode' | - | ||
| align='center' title='$14' | [[OpCode - TRB|TRB]] | | align='center' title='$14 Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]] | ||
| align='center' title='$15' | [[OpCode - ORA|ORA]] | | align='center' title='$15 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$16' | [[OpCode - ASL|ASL]] | | align='center' title='$16 Arithmetic Shift Left' | [[OpCode - ASL|ASL]] | ||
| align='center' title='$17' | [[OpCode - RMB1|RMB1]] | | align='center' title='$17 Reset Memory Bit 1' | [[OpCode - RMB1|RMB1]] | ||
| align='center' title='$18' | [[OpCode - CLC|CLC]] | | align='center' title='$18 Clear Carry' | [[OpCode - CLC|CLC]] | ||
| align='center' title='$19' | [[OpCode - ORA|ORA]] | | align='center' title='$19 Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$1A' | [[OpCode - INC|INC]] | | align='center' title='$1A Increment Accumulator' | [[OpCode - INC|INC]] | ||
| align='center' title='$1B Invalid OpCode' | - | | align='center' title='$1B Invalid OpCode' | - | ||
| align='center' title='$1C' | [[OpCode - TRB|TRB]] | | align='center' title='$1C Test and Reset Memory Bits with Accumulator' | [[OpCode - TRB|TRB]] | ||
| align='center' title='$1D' | [[OpCode - ORA|ORA]] | | align='center' title='$1D Bitwise OR with Accumulator' | [[OpCode - ORA|ORA]] | ||
| align='center' title='$1E' | [[OpCode - ASL|ASL]] | | align='center' title='$1E Arithmetic Shift Left' | [[OpCode - ASL|ASL]] | ||
| align='center' title='$1F' | [[OpCode - BBR1|BBR1]] | | align='center' title='$1F Branch if Bit 1 Reset' | [[OpCode - BBR1|BBR1]] | ||
|- | |- | ||
! 2x | ! 2x | ||
| align='center' title='$20' | [[OpCode - JSR|JSR]] | | align='center' title='$20 Jump to Subroutine' | [[OpCode - JSR|JSR]] | ||
| align='center' title='$21' | [[OpCode - AND|AND]] | | align='center' title='$21 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$22 Invalid OpCode' | - | | align='center' title='$22 Invalid OpCode' | - | ||
| align='center' title='$23 Invalid OpCode' | - | | align='center' title='$23 Invalid OpCode' | - | ||
| align='center' title='$24' | [[OpCode - BIT|BIT]] | | align='center' title='$24 Test Bits' | [[OpCode - BIT|BIT]] | ||
| align='center' title='$25' | [[OpCode - AND|AND]] | | align='center' title='$25 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$26' | [[OpCode - ROL|ROL]] | | align='center' title='$26 Rotate Left' | [[OpCode - ROL|ROL]] | ||
| align='center' title='$27' | [[OpCode - RMB2|RMB2]] | | align='center' title='$27 Reset Memory Bit 2' | [[OpCode - RMB2|RMB2]] | ||
| align='center' title='$28' | [[OpCode - PLP|PLP]] | | align='center' title='$28 Pull Processor Status from Stack' | [[OpCode - PLP|PLP]] | ||
| align='center' title='$29' | [[OpCode - AND|AND]] | | align='center' title='$29 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$2A' | [[OpCode - ROL|ROL]] | | align='center' title='$2A Rotate Left' | [[OpCode - ROL|ROL]] | ||
| align='center' title='$2B Invalid OpCode' | - | | align='center' title='$2B Invalid OpCode' | - | ||
| align='center' title='$2C' | [[OpCode - BIT|BIT]] | | align='center' title='$2C Test Bits' | [[OpCode - BIT|BIT]] | ||
| align='center' title='$2D' | [[OpCode - AND|AND]] | | align='center' title='$2D Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$2E' | [[OpCode - ROL|ROL]] | | align='center' title='$2E Rotate Left' | [[OpCode - ROL|ROL]] | ||
| align='center' title='$2F' | [[OpCode - BBR2|BBR2]] | | align='center' title='$2F Branch if Bit 2 Reset' | [[OpCode - BBR2|BBR2]] | ||
|- | |- | ||
! 3x | ! 3x | ||
| align='center' title='$30' | [[OpCode - BMI|BMI]] | | align='center' title='$30 Branch on Minus' | [[OpCode - BMI|BMI]] | ||
| align='center' title='$31' | [[OpCode - AND|AND]] | | align='center' title='$31 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$32' | [[OpCode - AND|AND]] | | align='center' title='$32 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$33 Invalid OpCode' | - | | align='center' title='$33 Invalid OpCode' | - | ||
| align='center' title='$34' | [[OpCode - BIT|BIT]] | | align='center' title='$34 Test Bits' | [[OpCode - BIT|BIT]] | ||
| align='center' title='$35' | [[OpCode - AND|AND]] | | align='center' title='$35 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$36' | [[OpCode - ROL|ROL]] | | align='center' title='$36 Rotate Left' | [[OpCode - ROL|ROL]] | ||
| align='center' title='$37' | [[OpCode - RMB3|RMB3]] | | align='center' title='$37 Reset Memory Bit 3' | [[OpCode - RMB3|RMB3]] | ||
| align='center' title='$38' | [[OpCode - SEC|SEC]] | | align='center' title='$38 Set Carry' | [[OpCode - SEC|SEC]] | ||
| align='center' title='$39' | [[OpCode - AND|AND]] | | align='center' title='$39 Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$3A' | [[OpCode - DEC|DEC]] | | align='center' title='$3A Decrement Accumulator' | [[OpCode - DEC|DEC]] | ||
| align='center' title='$3B Invalid OpCode' | - | | align='center' title='$3B Invalid OpCode' | - | ||
| align='center' title='$3C' | [[OpCode - BIT|BIT]] | | align='center' title='$3C Test Bits' | [[OpCode - BIT|BIT]] | ||
| align='center' title='$3D' | [[OpCode - AND|AND]] | | align='center' title='$3D Bitwise AND with Accumulator' | [[OpCode - AND|AND]] | ||
| align='center' title='$3E' | [[OpCode - ROL|ROL]] | | align='center' title='$3E Rotate Left' | [[OpCode - ROL|ROL]] | ||
| align='center' title='$3F' | [[OpCode - BBR3|BBR3]] | | align='center' title='$3F Branch if Bit 3 Reset' | [[OpCode - BBR3|BBR3]] | ||
|- | |- | ||
! 4x | ! 4x | ||
| align='center' title='$40' | [[OpCode - RTI|RTI]] | | align='center' title='$40 Return from Interrupt' | [[OpCode - RTI|RTI]] | ||
| align='center' title='$41' | [[OpCode - EOR|EOR]] | | align='center' title='$41 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$42 Invalid OpCode' | - | | align='center' title='$42 Invalid OpCode' | - | ||
| align='center' title='$43 Invalid OpCode' | - | | align='center' title='$43 Invalid OpCode' | - | ||
| align='center' title='$44 Invalid OpCode' | - | | align='center' title='$44 Invalid OpCode' | - | ||
| align='center' title='$45' | [[OpCode - EOR|EOR]] | | align='center' title='$45 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$46' | [[OpCode - LSR|LSR]] | | align='center' title='$46 Logical Shift Right' | [[OpCode - LSR|LSR]] | ||
| align='center' title='$47' | [[OpCode - RMB4|RMB4]] | | align='center' title='$47 Reset Memory Bit 4' | [[OpCode - RMB4|RMB4]] | ||
| align='center' title='$48' | [[OpCode - PHA|PHA]] | | align='center' title='$48 Push Accumulator to Stack' | [[OpCode - PHA|PHA]] | ||
| align='center' title='$49' | [[OpCode - EOR|EOR]] | | align='center' title='$49 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$4A' | [[OpCode - LSR|LSR]] | | align='center' title='$4A Logical Shift Right' | [[OpCode - LSR|LSR]] | ||
| align='center' title='$4B Invalid OpCode' | - | | align='center' title='$4B Invalid OpCode' | - | ||
| align='center' title='$4C' | [[OpCode - JMP|JMP]] | | align='center' title='$4C Jump' | [[OpCode - JMP|JMP]] | ||
| align='center' title='$4D' | [[OpCode - EOR|EOR]] | | align='center' title='$4D Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$4E' | [[OpCode - LSR|LSR]] | | align='center' title='$4E Logical Shift Right' | [[OpCode - LSR|LSR]] | ||
| align='center' title='$4F' | [[OpCode - BBR4|BBR4]] | | align='center' title='$4F Branch if Bit 4 Reset' | [[OpCode - BBR4|BBR4]] | ||
|- | |- | ||
! 5x | ! 5x | ||
| align='center' title='$50' | [[OpCode - BVC|BVC]] | | align='center' title='$50 Branch on Overflow Clear' | [[OpCode - BVC|BVC]] | ||
| align='center' title='$51' | [[OpCode - EOR|EOR]] | | align='center' title='$51 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$52' | [[OpCode - EOR|EOR]] | | align='center' title='$52 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$53 Invalid OpCode' | - | | align='center' title='$53 Invalid OpCode' | - | ||
| align='center' title='$54 Invalid OpCode' | - | | align='center' title='$54 Invalid OpCode' | - | ||
| align='center' title='$55' | [[OpCode - EOR|EOR]] | | align='center' title='$55 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$56' | [[OpCode - LSR|LSR]] | | align='center' title='$56 Logical Shift Right' | [[OpCode - LSR|LSR]] | ||
| align='center' title='$57' | [[OpCode - RMB5|RMB5]] | | align='center' title='$57 Reset Memory Bit 5' | [[OpCode - RMB5|RMB5]] | ||
| align='center' title='$58' | [[OpCode - CLI|CLI]] | | align='center' title='$58 Clear Interrupt' | [[OpCode - CLI|CLI]] | ||
| align='center' title='$59' | [[OpCode - EOR|EOR]] | | align='center' title='$59 Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$5A' | [[OpCode - PHY|PHY]] | | align='center' title='$5A Push Y Register to Stack' | [[OpCode - PHY|PHY]] | ||
| align='center' title='$5B Invalid OpCode' | - | | align='center' title='$5B Invalid OpCode' | - | ||
| align='center' title='$5C Invalid OpCode' | - | | align='center' title='$5C Invalid OpCode' | - | ||
| align='center' title='$5D' | [[OpCode - EOR|EOR]] | | align='center' title='$5D Bitwise Exclusive OR' | [[OpCode - EOR|EOR]] | ||
| align='center' title='$5E' | [[OpCode - LSR|LSR]] | | align='center' title='$5E Logical Shift Right' | [[OpCode - LSR|LSR]] | ||
| align='center' title='$5F' | [[OpCode - BBR5|BBR5]] | | align='center' title='$5F Branch if Bit 5 Reset' | [[OpCode - BBR5|BBR5]] | ||
|- | |- | ||
! 6x | ! 6x | ||
| align='center' title='$60' | [[OpCode - RTS|RTS]] | | align='center' title='$60 Return from Subroutine' | [[OpCode - RTS|RTS]] | ||
| align='center' title='$61' | [[OpCode - ADC|ADC]] | | align='center' title='$61 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$62 Invalid OpCode' | - | | align='center' title='$62 Invalid OpCode' | - | ||
| align='center' title='$63 Invalid OpCode' | - | | align='center' title='$63 Invalid OpCode' | - | ||
| align='center' title='$64' | [[OpCode - STZ|STZ]] | | align='center' title='$64 Store Zero to Memory' | [[OpCode - STZ|STZ]] | ||
| align='center' title='$65' | [[OpCode - ADC|ADC]] | | align='center' title='$65 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$66' | [[OpCode - ROR|ROR]] | | align='center' title='$66 Rotate Right' | [[OpCode - ROR|ROR]] | ||
| align='center' title='$67' | [[OpCode - RMB6|RMB6]] | | align='center' title='$67 Reset Memory Bit 6' | [[OpCode - RMB6|RMB6]] | ||
| align='center' title='$68' | [[OpCode - PLA|PLA]] | | align='center' title='$68 Pull Stack to Accumulator' | [[OpCode - PLA|PLA]] | ||
| align='center' title='$69' | [[OpCode - ADC|ADC]] | | align='center' title='$69 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$6A' | [[OpCode - ROR|ROR]] | | align='center' title='$6A Rotate Right' | [[OpCode - ROR|ROR]] | ||
| align='center' title='$6B Invalid OpCode' | - | | align='center' title='$6B Invalid OpCode' | - | ||
| align='center' title='$6C' | [[OpCode - JMP|JMP]] | | align='center' title='$6C Jump' | [[OpCode - JMP|JMP]] | ||
| align='center' title='$6D' | [[OpCode - ADC|ADC]] | | align='center' title='$6D Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$6E' | [[OpCode - ROR|ROR]] | | align='center' title='$6E Rotate Right' | [[OpCode - ROR|ROR]] | ||
| align='center' title='$6F' | [[OpCode - BBR6|BBR6]] | | align='center' title='$6F Branch if Bit 6 Reset' | [[OpCode - BBR6|BBR6]] | ||
|- | |- | ||
! 7x | ! 7x | ||
| align='center' title='$70' | [[OpCode - BVS|BVS]] | | align='center' title='$70 Branch on Overflow Set' | [[OpCode - BVS|BVS]] | ||
| align='center' title='$71' | [[OpCode - ADC|ADC]] | | align='center' title='$71 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$72' | [[OpCode - ADC|ADC]] | | align='center' title='$72 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$73 Invalid OpCode' | - | | align='center' title='$73 Invalid OpCode' | - | ||
| align='center' title='$74' | [[OpCode - STZ|STZ]] | | align='center' title='$74 Store Zero to Memory' | [[OpCode - STZ|STZ]] | ||
| align='center' title='$75' | [[OpCode - ADC|ADC]] | | align='center' title='$75 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$76' | [[OpCode - ROR|ROR]] | | align='center' title='$76 Rotate Right' | [[OpCode - ROR|ROR]] | ||
| align='center' title='$77' | [[OpCode - RMB7|RMB7]] | | align='center' title='$77 Reset Memory Bit 7' | [[OpCode - RMB7|RMB7]] | ||
| align='center' title='$78' | [[OpCode - SEI|SEI]] | | align='center' title='$78 Set Interrupt' | [[OpCode - SEI|SEI]] | ||
| align='center' title='$79' | [[OpCode - ADC|ADC]] | | align='center' title='$79 Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$7A' | [[OpCode - PLY|PLY]] | | align='center' title='$7A Pull Register Y from Stack' | [[OpCode - PLY|PLY]] | ||
| align='center' title='$7B Invalid OpCode' | - | | align='center' title='$7B Invalid OpCode' | - | ||
| align='center' title='$7C' | [[OpCode - JMP|JMP]] | | align='center' title='$7C Jump' | [[OpCode - JMP|JMP]] | ||
| align='center' title='$7D' | [[OpCode - ADC|ADC]] | | align='center' title='$7D Add with Carry' | [[OpCode - ADC|ADC]] | ||
| align='center' title='$7E' | [[OpCode - ROR|ROR]] | | align='center' title='$7E Rotate Right' | [[OpCode - ROR|ROR]] | ||
| align='center' title='$7F' | [[OpCode - BBR7|BBR7]] | | align='center' title='$7F Branch if Bit 7 Reset' | [[OpCode - BBR7|BBR7]] | ||
|- | |- | ||
! 8x | ! 8x | ||
| align='center' title='$80' | [[OpCode - BRA|BRA]] | | align='center' title='$80 Branch Always' | [[OpCode - BRA|BRA]] | ||
| align='center' title='$81' | [[OpCode - STA|STA]] | | align='center' title='$81 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$82 Invalid OpCode' | - | | align='center' title='$82 Invalid OpCode' | - | ||
| align='center' title='$83 Invalid OpCode' | - | | align='center' title='$83 Invalid OpCode' | - | ||
| align='center' title='$84' | [[OpCode - STY|STY]] | | align='center' title='$84 Store Y Register' | [[OpCode - STY|STY]] | ||
| align='center' title='$85' | [[OpCode - STA|STA]] | | align='center' title='$85 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$86' | [[OpCode - STX|STX]] | | align='center' title='$86 Store X Register' | [[OpCode - STX|STX]] | ||
| align='center' title='$87' | [[OpCode - SMB0|SMB0]] | | align='center' title='$87 Set Memory Bit 0' | [[OpCode - SMB0|SMB0]] | ||
| align='center' title='$88' | [[OpCode - DEY|DEY]] | | align='center' title='$88 Decrement Y Register' | [[OpCode - DEY|DEY]] | ||
| align='center' title='$89' | [[OpCode - BIT|BIT]] | | align='center' title='$89 Test Bits' | [[OpCode - BIT|BIT]] | ||
| align='center' title='$8A' | [[OpCode - TXA|TXA]] | | align='center' title='$8A Transfer X Register to Accumulator' | [[OpCode - TXA|TXA]] | ||
| align='center' title='$8B Invalid OpCode' | - | | align='center' title='$8B Invalid OpCode' | - | ||
| align='center' title='$8C' | [[OpCode - STY|STY]] | | align='center' title='$8C Store Y Register' | [[OpCode - STY|STY]] | ||
| align='center' title='$8D' | [[OpCode - STA|STA]] | | align='center' title='$8D Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$8E' | [[OpCode - STX|STX]] | | align='center' title='$8E Store X Register' | [[OpCode - STX|STX]] | ||
| align='center' title='$8F' | [[OpCode - BBS0|BBS0]] | | align='center' title='$8F Branch if Bit 0 Set' | [[OpCode - BBS0|BBS0]] | ||
|- | |- | ||
! 9x | ! 9x | ||
| align='center' title='$90' | [[OpCode - BCC|BCC]] | | align='center' title='$90 Branch on Carry Clear' | [[OpCode - BCC|BCC]] | ||
| align='center' title='$91' | [[OpCode - STA|STA]] | | align='center' title='$91 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$92' | [[OpCode - STA|STA]] | | align='center' title='$92 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$93 Invalid OpCode' | - | | align='center' title='$93 Invalid OpCode' | - | ||
| align='center' title='$94' | [[OpCode - STY|STY]] | | align='center' title='$94 Store Y Register' | [[OpCode - STY|STY]] | ||
| align='center' title='$95' | [[OpCode - STA|STA]] | | align='center' title='$95 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$96' | [[OpCode - STX|STX]] | | align='center' title='$96 Store X Register' | [[OpCode - STX|STX]] | ||
| align='center' title='$97' | [[OpCode - SMB1|SMB1]] | | align='center' title='$97 Set Memory Bit 1' | [[OpCode - SMB1|SMB1]] | ||
| align='center' title='$98' | [[OpCode - TYA|TYA]] | | align='center' title='$98 Transfer Y Register to Accumulator' | [[OpCode - TYA|TYA]] | ||
| align='center' title='$99' | [[OpCode - STA|STA]] | | align='center' title='$99 Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$9A' | [[OpCode - TXS|TXS]] | | align='center' title='$9A Transfer X Register to Stack Pointer' | [[OpCode - TXS|TXS]] | ||
| align='center' title='$9B Invalid OpCode' | - | | align='center' title='$9B Invalid OpCode' | - | ||
| align='center' title='$9C' | [[OpCode - STZ|STZ]] | | align='center' title='$9C Store Zero to Memory' | [[OpCode - STZ|STZ]] | ||
| align='center' title='$9D' | [[OpCode - STA|STA]] | | align='center' title='$9D Store Accumulator' | [[OpCode - STA|STA]] | ||
| align='center' title='$9E' | [[OpCode - STZ|STZ]] | | align='center' title='$9E Store Zero to Memory' | [[OpCode - STZ|STZ]] | ||
| align='center' title='$9F' | [[OpCode - BBS1|BBS1]] | | align='center' title='$9F Branch if Bit 1 Set' | [[OpCode - BBS1|BBS1]] | ||
|- | |- | ||
! Ax | ! Ax | ||
| align='center' title='$A0' | [[OpCode - LDY|LDY]] | | align='center' title='$A0 Load Y Register' | [[OpCode - LDY|LDY]] | ||
| align='center' title='$A1' | [[OpCode - LDA|LDA]] | | align='center' title='$A1 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$A2' | [[OpCode - LDX|LDX]] | | align='center' title='$A2 Load X Register' | [[OpCode - LDX|LDX]] | ||
| align='center' title='$A3 Invalid OpCode' | - | | align='center' title='$A3 Invalid OpCode' | - | ||
| align='center' title='$A4' | [[OpCode - LDY|LDY]] | | align='center' title='$A4 Load Y Register' | [[OpCode - LDY|LDY]] | ||
| align='center' title='$A5' | [[OpCode - LDA|LDA]] | | align='center' title='$A5 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$A6' | [[OpCode - LDX|LDX]] | | align='center' title='$A6 Load X Register' | [[OpCode - LDX|LDX]] | ||
| align='center' title='$A7' | [[OpCode - SMB2|SMB2]] | | align='center' title='$A7 Set Memory Bit 2' | [[OpCode - SMB2|SMB2]] | ||
| align='center' title='$A8' | [[OpCode - TAY|TAY]] | | align='center' title='$A8 Transfer Accumulator to Y Register' | [[OpCode - TAY|TAY]] | ||
| align='center' title='$A9' | [[OpCode - LDA|LDA]] | | align='center' title='$A9 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$AA' | [[OpCode - TAX|TAX]] | | align='center' title='$AA Transfer Accumulator to X Register' | [[OpCode - TAX|TAX]] | ||
| align='center' title='$AB Invalid OpCode' | - | | align='center' title='$AB Invalid OpCode' | - | ||
| align='center' title='$AC' | [[OpCode - LDY|LDY]] | | align='center' title='$AC Load Y Register' | [[OpCode - LDY|LDY]] | ||
| align='center' title='$AD' | [[OpCode - LDA|LDA]] | | align='center' title='$AD Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$AE' | [[OpCode - LDX|LDX]] | | align='center' title='$AE Load X Register' | [[OpCode - LDX|LDX]] | ||
| align='center' title='$AF' | [[OpCode - BBS2|BBS2]] | | align='center' title='$AF Branch if Bit 2 Set' | [[OpCode - BBS2|BBS2]] | ||
|- | |- | ||
! Bx | ! Bx | ||
| align='center' title='$B0' | [[OpCode - BCS|BCS]] | | align='center' title='$B0 Branch on Carry Set' | [[OpCode - BCS|BCS]] | ||
| align='center' title='$B1' | [[OpCode - LDA|LDA]] | | align='center' title='$B1 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$B2' | [[OpCode - LDA|LDA]] | | align='center' title='$B2 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$B3 Invalid OpCode' | - | | align='center' title='$B3 Invalid OpCode' | - | ||
| align='center' title='$B4' | [[OpCode - LDY|LDY]] | | align='center' title='$B4 Load Y Register' | [[OpCode - LDY|LDY]] | ||
| align='center' title='$B5' | [[OpCode - LDA|LDA]] | | align='center' title='$B5 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$B6' | [[OpCode - LDX|LDX]] | | align='center' title='$B6 Load X Register' | [[OpCode - LDX|LDX]] | ||
| align='center' title='$B7' | [[OpCode - SMB3|SMB3]] | | align='center' title='$B7 Set Memory Bit 3' | [[OpCode - SMB3|SMB3]] | ||
| align='center' title='$B8' | [[OpCode - CLV|CLV]] | | align='center' title='$B8 Clear Overflow' | [[OpCode - CLV|CLV]] | ||
| align='center' title='$B9' | [[OpCode - LDA|LDA]] | | align='center' title='$B9 Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$BA' | [[OpCode - TSX|TSX]] | | align='center' title='$BA Transfer Stack Pointer to X Register' | [[OpCode - TSX|TSX]] | ||
| align='center' title='$BB Invalid OpCode' | - | | align='center' title='$BB Invalid OpCode' | - | ||
| align='center' title='$BC' | [[OpCode - LDY|LDY]] | | align='center' title='$BC Load Y Register' | [[OpCode - LDY|LDY]] | ||
| align='center' title='$BD' | [[OpCode - LDA|LDA]] | | align='center' title='$BD Load Accumulator' | [[OpCode - LDA|LDA]] | ||
| align='center' title='$BE' | [[OpCode - LDX|LDX]] | | align='center' title='$BE Load X Register' | [[OpCode - LDX|LDX]] | ||
| align='center' title='$BF' | [[OpCode - BBS3|BBS3]] | | align='center' title='$BF Branch if Bit 3 Set' | [[OpCode - BBS3|BBS3]] | ||
|- | |- | ||
! Cx | ! Cx | ||
| align='center' title='$C0' | [[OpCode - CPY|CPY]] | | align='center' title='$C0 Compare with Y Register' | [[OpCode - CPY|CPY]] | ||
| align='center' title='$C1' | [[OpCode - CMP|CMP]] | | align='center' title='$C1 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$C2 Invalid OpCode' | - | | align='center' title='$C2 Invalid OpCode' | - | ||
| align='center' title='$C3 Invalid OpCode' | - | | align='center' title='$C3 Invalid OpCode' | - | ||
| align='center' title='$C4' | [[OpCode - CPY|CPY]] | | align='center' title='$C4 Compare with Y Register' | [[OpCode - CPY|CPY]] | ||
| align='center' title='$C5' | [[OpCode - CMP|CMP]] | | align='center' title='$C5 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$C6' | [[OpCode - DEC|DEC]] | | align='center' title='$C6 Decrement Memory' | [[OpCode - DEC|DEC]] | ||
| align='center' title='$C7' | [[OpCode - SMB4|SMB4]] | | align='center' title='$C7 Set Memory Bit 4' | [[OpCode - SMB4|SMB4]] | ||
| align='center' title='$C8' | [[OpCode - INY|INY]] | | align='center' title='$C8 Increment Y Register' | [[OpCode - INY|INY]] | ||
| align='center' title='$C9' | [[OpCode - CMP|CMP]] | | align='center' title='$C9 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$CA' | [[OpCode - DEX|DEX]] | | align='center' title='$CA Decrement X Register' | [[OpCode - DEX|DEX]] | ||
| align='center' title='$CB' | [[OpCode - WAI|WAI]] | | align='center' title='$CB Wait for Interrupt' | [[OpCode - WAI|WAI]] | ||
| align='center' title='$CC' | [[OpCode - CPY|CPY]] | | align='center' title='$CC Compare with Y Register' | [[OpCode - CPY|CPY]] | ||
| align='center' title='$CD' | [[OpCode - CMP|CMP]] | | align='center' title='$CD Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$CE' | [[OpCode - DEC|DEC]] | | align='center' title='$CE Decrement Memory' | [[OpCode - DEC|DEC]] | ||
| align='center' title='$CF' | [[OpCode - BBS4|BBS4]] | | align='center' title='$CF Branch if Bit 4 Set' | [[OpCode - BBS4|BBS4]] | ||
|- | |- | ||
! Dx | ! Dx | ||
| align='center' title='$D0' | [[OpCode - BNE|BNE]] | | align='center' title='$D0 Branch on Not Equal' | [[OpCode - BNE|BNE]] | ||
| align='center' title='$D1' | [[OpCode - CMP|CMP]] | | align='center' title='$D1 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$D2' | [[OpCode - CMP|CMP]] | | align='center' title='$D2 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$D3 Invalid OpCode' | - | | align='center' title='$D3 Invalid OpCode' | - | ||
| align='center' title='$D4 Invalid OpCode' | - | | align='center' title='$D4 Invalid OpCode' | - | ||
| align='center' title='$D5' | [[OpCode - CMP|CMP]] | | align='center' title='$D5 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$D6' | [[OpCode - DEC|DEC]] | | align='center' title='$D6 Decrement Memory' | [[OpCode - DEC|DEC]] | ||
| align='center' title='$D7' | [[OpCode - SMB5|SMB5]] | | align='center' title='$D7 Set Memory Bit 5' | [[OpCode - SMB5|SMB5]] | ||
| align='center' title='$D8' | [[OpCode - CLD|CLD]] | | align='center' title='$D8 Clear Decimal' | [[OpCode - CLD|CLD]] | ||
| align='center' title='$D9' | [[OpCode - CMP|CMP]] | | align='center' title='$D9 Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$DA' | [[OpCode - PHX|PHX]] | | align='center' title='$DA Push X Register to Stack' | [[OpCode - PHX|PHX]] | ||
| align='center' title='$DB' | [[OpCode - STP|STP]] | | align='center' title='$DB Stop until CPU Reset' | [[OpCode - STP|STP]] | ||
| align='center' title='$DC Invalid OpCode' | - | | align='center' title='$DC Invalid OpCode' | - | ||
| align='center' title='$DD' | [[OpCode - CMP|CMP]] | | align='center' title='$DD Compare with Accumulator' | [[OpCode - CMP|CMP]] | ||
| align='center' title='$DE' | [[OpCode - DEC|DEC]] | | align='center' title='$DE Decrement Memory' | [[OpCode - DEC|DEC]] | ||
| align='center' title='$DF' | [[OpCode - BBS5|BBS5]] | | align='center' title='$DF Branch if Bit 5 Set' | [[OpCode - BBS5|BBS5]] | ||
|- | |- | ||
! Ex | ! Ex | ||
| align='center' title='$E0' | [[OpCode - CPX|CPX]] | | align='center' title='$E0 Compare with X Register' | [[OpCode - CPX|CPX]] | ||
| align='center' title='$E1' | [[OpCode - SBC|SBC]] | | align='center' title='$E1 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$E2 Invalid OpCode' | - | | align='center' title='$E2 Invalid OpCode' | - | ||
| align='center' title='$E3 Invalid OpCode' | - | | align='center' title='$E3 Invalid OpCode' | - | ||
| align='center' title='$E4' | [[OpCode - CPX|CPX]] | | align='center' title='$E4 Compare with X Register' | [[OpCode - CPX|CPX]] | ||
| align='center' title='$E5' | [[OpCode - SBC|SBC]] | | align='center' title='$E5 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$E6' | [[OpCode - INC|INC]] | | align='center' title='$E6 Increment Memory' | [[OpCode - INC|INC]] | ||
| align='center' title='$E7' | [[OpCode - SMB6|SMB6]] | | align='center' title='$E7 Set Memory Bit 6' | [[OpCode - SMB6|SMB6]] | ||
| align='center' title='$E8' | [[OpCode - INX|INX]] | | align='center' title='$E8 Increment X Register' | [[OpCode - INX|INX]] | ||
| align='center' title='$E9' | [[OpCode - SBC|SBC]] | | align='center' title='$E9 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$EA' | [[OpCode - NOP|NOP]] | | align='center' title='$EA No Operation' | [[OpCode - NOP|NOP]] | ||
| align='center' title='$EB Invalid OpCode' | - | | align='center' title='$EB Invalid OpCode' | - | ||
| align='center' title='$EC' | [[OpCode - CPX|CPX]] | | align='center' title='$EC Compare with X Register' | [[OpCode - CPX|CPX]] | ||
| align='center' title='$ED' | [[OpCode - SBC|SBC]] | | align='center' title='$ED Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$EE' | [[OpCode - INC|INC]] | | align='center' title='$EE Increment Memory' | [[OpCode - INC|INC]] | ||
| align='center' title='$EF' | [[OpCode - BBS6|BBS6]] | | align='center' title='$EF Branch if Bit 6 Set' | [[OpCode - BBS6|BBS6]] | ||
|- | |- | ||
! Fx | ! Fx | ||
| align='center' title='$F0' | [[OpCode - BEQ|BEQ]] | | align='center' title='$F0 Branch on Equal' | [[OpCode - BEQ|BEQ]] | ||
| align='center' title='$F1' | [[OpCode - SBC|SBC]] | | align='center' title='$F1 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$F2' | [[OpCode - SBC|SBC]] | | align='center' title='$F2 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$F3 Invalid OpCode' | - | | align='center' title='$F3 Invalid OpCode' | - | ||
| align='center' title='$F4 Invalid OpCode' | - | | align='center' title='$F4 Invalid OpCode' | - | ||
| align='center' title='$F5' | [[OpCode - SBC|SBC]] | | align='center' title='$F5 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$F6' | [[OpCode - INC|INC]] | | align='center' title='$F6 Increment Memory' | [[OpCode - INC|INC]] | ||
| align='center' title='$F7' | [[OpCode - SMB7|SMB7]] | | align='center' title='$F7 Set Memory Bit 7' | [[OpCode - SMB7|SMB7]] | ||
| align='center' title='$F8' | [[OpCode - SED|SED]] | | align='center' title='$F8 Set Decimal' | [[OpCode - SED|SED]] | ||
| align='center' title='$F9' | [[OpCode - SBC|SBC]] | | align='center' title='$F9 Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$FA' | [[OpCode - PLX|PLX]] | | align='center' title='$FA Pull X Register from Stack' | [[OpCode - PLX|PLX]] | ||
| align='center' title='$FB Invalid OpCode' | - | | align='center' title='$FB Invalid OpCode' | - | ||
| align='center' title='$FC Invalid OpCode' | - | | align='center' title='$FC Invalid OpCode' | - | ||
| align='center' title='$FD' | [[OpCode - SBC|SBC]] | | align='center' title='$FD Subtract with Carry' | [[OpCode - SBC|SBC]] | ||
| align='center' title='$FE' | [[OpCode - INC|INC]] | | align='center' title='$FE Increment Memory' | [[OpCode - INC|INC]] | ||
| align='center' title='$FF' | [[OpCode - BBS7|BBS7]] | | align='center' title='$FF Branch if Bit 7 Set' | [[OpCode - BBS7|BBS7]] | ||
|} | |} | ||
