User contributions for NerdOfEpic

30 January 2024

• 19:4619:46, 30 January 2024 diff hist −10‎ Memory Region - PPU Control Page ‎No edit summary current
• 19:4519:45, 30 January 2024 diff hist +49‎ N User:NerdOfEpic/basic.css ‎ Created page with ".mono { font-family: monospace; font-size: 150% }" current
• 18:2918:29, 30 January 2024 diff hist +73‎ Chip - 65C02 CPU ‎No edit summary

29 January 2024

• 19:4919:49, 29 January 2024 diff hist +4,312‎ 65C02 CPU OpCodes ‎No edit summary
• 19:4019:40, 29 January 2024 diff hist +7,368‎ 65C02 CPU OpCodes ‎No edit summary
• 18:5818:58, 29 January 2024 diff hist +6‎ Chip - 65C02 CPU ‎No edit summary
• 18:5818:58, 29 January 2024 diff hist 0‎ m 65C02 CPU OpCodes ‎ NerdOfEpic moved page CPU OpCodes to 65C02 CPU OpCodes without leaving a redirect

28 January 2024

• 20:0420:04, 28 January 2024 diff hist +6,257‎ N 65C02 CPU OpCodes ‎ Created page with "{| class='wikitable' | ! width='25' | 0 ! width='25' | 1 ! width='25' | 2 ! width='25' | 3 ! width='25' | 4 ! width='25' | 5 ! width='25' | 6 ! width='25' | 7 ! width='25' | 8 ! width='25' | 9 ! width='25' | A ! width='25' | B ! width='25' | C ! width='25' | D ! width='25' | E ! width='25' | F |- ! 0x | align='center' | BRK | align='center' | ORA | align='center' | - | align='center' | - | align='center' | TRB | align='center' | ORA | align='center' | ASL | align='center..."
• 19:1419:14, 28 January 2024 diff hist +51‎ Chip - 65C02 CPU ‎No edit summary
• 19:1219:12, 28 January 2024 diff hist 0‎ User:NerdOfEpic/memory-regions.css ‎No edit summary current
• 19:1119:11, 28 January 2024 diff hist +24‎ User:NerdOfEpic/memory-regions.css ‎No edit summary
• 19:0919:09, 28 January 2024 diff hist +20‎ Memory Region - PPU Background Tile Table ‎No edit summary current
• 19:0919:09, 28 January 2024 diff hist +949‎ N Memory Region - PPU Sprite Tile Table ‎ Created page with "'''Address Range:''' <span class='mono'>$6000 - $7FFF</span> Size: 8,192 bytes First, set the Extended RAM Select register in the Control Page to bank 255 to redirect Extended RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as data in the Sprite Tile Table. This data is arranged into 8x8 tiles that use 8, 16, 24, 32, 40..."
• 19:0819:08, 28 January 2024 diff hist +958‎ N Memory Region - PPU Background Tile Table ‎ Created page with "'''Address Range:''' <span class='mono'>$4000 - $5FFF</span> Size: 8,192 bytes First, set the Extended RAM Select register in the Control Page to bank 255 to redirect Extended RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as data in the Background Tile Table. This data is arranged into 8x8 tiles that use 8, 16, 24, 32..."
• 18:5718:57, 28 January 2024 diff hist +49‎ Memory Region - PPU Fixed Name Table ‎No edit summary
• 18:5718:57, 28 January 2024 diff hist +585‎ N Memory Region - PPU Main Name Table ‎ Created page with "'''Address Range:''' <span class='mono'>$2000 - $3FFF</span> Size: 8,192 bytes First, use the Main RAM Select register in the Control Page to redirect Main RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as data in the Main Name Table. This data is arranged into 2-byte groups that each how a 8x8 tile is displayed on the screen..."
• 18:5518:55, 28 January 2024 diff hist +586‎ N Memory Region - PPU Fixed Name Table ‎ Created page with "'''Address Range:''' <span class='mono'>$1800 - $1FFF</span> Size: 2,048 bytes First, use the Main RAM Select register in the Control Page to redirect Main RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as data in the Fixed Name Table. This data is arranged into 2-byte groups that each how a 8x8 tile is displayed on the screen..."

27 January 2024

• 21:3021:30, 27 January 2024 diff hist +546‎ N Memory Region - PPU Sprite Table ‎ Created page with "'''Address Range:''' <span class='mono'>$1400 - $17FF</span> Size: 1,024 bytes First, use the Main RAM Select register in the Control Page to redirect Main RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as data in the Sprite Table. This data is arranged into 4-byte groups that each define where an 8x8 tile is displayed on the screen. Ret..."
• 21:2421:24, 27 January 2024 diff hist 0‎ Memory Region - PPU Sprite Palettes ‎No edit summary
• 21:1621:16, 27 January 2024 diff hist +660‎ N Memory Region - PPU Sprite Palettes ‎ Created page with "'''Address Range:''' <span class='mono'>$08E0 - $13FF</span> Size: 1,536 bytes First, use the Main RAM Select register in the Control Page to redirect Main RAM to be redirected to the PPU. Then, writing data to this address range is interpreted as color data for the palettes that are used when rendering sprite graphics is set. This data is arranged into subpalettes based on the current Graphics Mo..."
• 21:1421:14, 27 January 2024 diff hist +333‎ Memory Region - PPU Background Palettes ‎No edit summary
• 21:0421:04, 27 January 2024 diff hist +331‎ N Memory Region - PPU Background Palettes ‎ Created page with "'''Address Range:''' <span class='mono'>$0800 - $0DFF</span> Size: 1,536 bytes Writing palette entries to this section of Main RAM sets up colors that will be used when rendering background graphics. Return to Memory Regions. {{#css:User:NerdOfEpic/builtin-palette.css}}"
• 20:5920:59, 27 January 2024 diff hist +442‎ N Memory Region - PPU Reserved ‎ Created page with "'''Address Range:''' <span class='mono'>$0300 - $07FF</span> Size: 1,280 bytes This section of Main RAM is not currently used by the PPU for anything, but is it reserved for possible future features. Data written to this section of memory is sent to the PPU, but is thrown away without further processing and cannot be retrieved. Return to Memory Regions. {{#css:User:NerdOfEpic/builtin-palette.css}}"
• 20:5520:55, 27 January 2024 diff hist +266‎ N Memory Region - PPU Control Page ‎ Created page with "'''Address Range:''' <span class='mono'>$0200 - $02FF</span> Size: 256 bytes The lower half of the Control Page is sent into the PPU and is used to control how graphics are generated. Return to Memory Regions. {{#css:User:NerdOfEpic/builtin-palette.css}}"
• 20:5320:53, 27 January 2024 diff hist +1‎ Memory Region - CPU High ROM ‎No edit summary
• 20:5220:52, 27 January 2024 diff hist +20‎ Memory Region - CPU High ROM ‎No edit summary
• 20:5220:52, 27 January 2024 diff hist +20‎ Memory Region - CPU Low ROM ‎No edit summary
• 20:5120:51, 27 January 2024 diff hist +20‎ Memory Region - CPU Extended RAM ‎No edit summary
• 20:5120:51, 27 January 2024 diff hist +20‎ Memory Region - CPU Main RAM ‎No edit summary
• 20:4920:49, 27 January 2024 diff hist +17‎ Memory Region - CPU Control Page ‎No edit summary
• 20:4920:49, 27 January 2024 diff hist +17‎ Memory Region - CPU Stack Page ‎No edit summary
• 20:4920:49, 27 January 2024 diff hist +17‎ Memory Region - CPU Zero Page ‎No edit summary
• 14:0414:04, 27 January 2024 diff hist +6‎ Memory Region - CPU High ROM ‎No edit summary
• 14:0314:03, 27 January 2024 diff hist +1‎ Memory Region - CPU High ROM ‎No edit summary
• 14:0314:03, 27 January 2024 diff hist +995‎ N Memory Region - CPU High ROM ‎ Created page with "'''Address Range:''' <span class='mono'>$8000 - $BFFF</span> The fourth 16KB of the address space is called High ROM. It represents a region of ROM that supports up to 256 banks which provide access to a total of 4MB of space for program and graphics data. Care must be taken to ensure access to this ROM is handled while the correct bank is active. This region of the address space, if available, is found in the cartridge. ''Important Note: If banking of High ROM is..."
• 13:5913:59, 27 January 2024 diff hist +824‎ N Memory Region - CPU Low ROM ‎ Created page with "'''Address Range:''' <span class='mono'>$8000 - $BFFF</span> The third 16KB of the address space called Low ROM. It represents a region of ROM that supports up to 256 banks which provide access to a total of 4MB of space for program and graphics data. Care must be taken to ensure access to this ROM is handled while the correct bank is active. This region of the address space, if available, is found in the cartridge. Banking of this region is controled by the Regi..."
• 13:5313:53, 27 January 2024 diff hist +606‎ N Memory Region - CPU Extended RAM ‎ Created page with "'''Address Range:''' <span class='mono'>$4000 - $7FFF</span> The second 16KB of RAM is called Extended RAM. It represents a region of RAM that is has 32 banks which provide access to a total of 512KB. Care must be taken to ensure access to this RAM is handled while the correct bank is active. This region can be redirected to the PPU using the Extended RAM Select register in the Control Page by selecting page 255. Banks 32-254..."
• 13:4813:48, 27 January 2024 diff hist +124‎ Memory Region - CPU Main RAM ‎No edit summary
• 13:4513:45, 27 January 2024 diff hist +781‎ N Memory Region - CPU Main RAM ‎ Created page with "'''Address Range:''' <span class='mono'>$0300 - $3FFF</span> In NerdConsole, the first 16KB of RAM is called Main RAM. It represents a region of RAM that is almost always available. Due to the nature of the 65C02 CPU the Zero Page and Stack Page must always be located in the same place. Banking this region of RAM would require complex hardware to constantly keep those pages up..."
• 13:3713:37, 27 January 2024 diff hist +310‎ N Memory Region - CPU Control Page ‎ Created page with "'''Address Range:''' <span class='mono'>$0200 - $02FF</span> To allow control over NerdConsole specific functionality like address region banking and loads of PPU related functionality, page 2 of RAM is used as the Control Page. Return to Memory Regions. {{#css:User:NerdOfEpic/builtin-palette.css}}"
• 13:3413:34, 27 January 2024 diff hist +1‎ Memory Region - CPU Stack Page ‎No edit summary
• 13:3213:32, 27 January 2024 diff hist +402‎ N Memory Region - CPU Stack Page ‎ Created page with "'''Address Range:''' <span class='mono'>$0100 - $01FF</span> To allow for calling subroutines, the CPU reserves page 1 of the address space for the call stack. It can be used for other purposes too, if needed, but most of the time it will be used automatically by the CPU to handle calling and returning from function calls. Return to Memory Regions. {{#css:User:NerdOfEpic/builtin-paltte.css}}"
• 13:2913:29, 27 January 2024 diff hist +643‎ Memory Region - CPU Zero Page ‎No edit summary
• 13:2313:23, 27 January 2024 diff hist +446‎ N Memory Region - PPU Inaccessible ‎ Created page with "There are sections of the CPU address space that are never redirected to the PPU. These areas are effectively inaccessible by the PPU for this reason. Specifically, the following sections of CPU addressable memory are inaccessible: * Zero Page * Stack Page * Low ROM * High ROM Return to Memory Regions." current
• 13:1513:15, 27 January 2024 diff hist 0‎ User:NerdOfEpic/memory-regions.css ‎No edit summary
• 13:1413:14, 27 January 2024 diff hist 0‎ User:NerdOfEpic/memory-regions.css ‎No edit summary
• 13:1213:12, 27 January 2024 diff hist 0‎ User:NerdOfEpic/memory-regions.css ‎No edit summary
• 13:1113:11, 27 January 2024 diff hist 0‎ User:NerdOfEpic/memory-regions.css ‎No edit summary

26 January 2024

• 14:2314:23, 26 January 2024 diff hist −46‎ Memory Regions ‎No edit summary current
• 14:2114:21, 26 January 2024 diff hist +5‎ N Memory Region - CPU Zero Page ‎ Created page with "Tacos"