Register - Tileset Cycle
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Tileset cycling is an automatic cycling that applies to all tiles if enabled. The tileset cycle speed is the number of frames to wait before the cycle advances. This has the effect of making the speed seem backwards since 0 is very fast and 255 is very slow. The maximum delay between cycle advances is 4.25 seconds.
Due to the nature of tilesets, a cycle limit value is also configurable to determine how many tilesets are involved in the cycling. The cycling goes between 0 and the limit.
Cycle Speed
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Byte 0 | S | S | S | S | S | S | S | S |
Key
- S - Cycle Speed [0-255]
Cycle Limit
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| Byte 0 | - | - | - | - | L | L | L | L |
Key
- S - Cycle Limit [0-15]
This register is a part of the Control Page.
